This application relies for priority upon Korean Patent Application No. 2000-45687, filed on Aug. 7, 2000, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to a nonvolatile memory device and more particularly to a row decoder employed in the non-volatile semiconductor memory device.
Generally, semiconductor memory devices for storing data are classified into volatile and non-volatile, the latter class including flash memory devices. In a flash semiconductor memory device its memory cells can be electrically programmed and data stored in the memory cells can be electrically erased. According to an operation of a normal flash memory device, programming of the memory cells is conducted by using the injection of hot electrons to a floating gate from a drain region and an adjacent channel region. To program the cells, a voltage of about 5V is applied to the drain region to generate hot electrons while a source region and a substrate (or a bulk) are grounded in common, and a high voltage of about 9V is applied to a control gate. As such, since the floating gate in the programmed memory cells is filled with negative charges, a threshold voltage of the memory cells is increased. To the contrary, to erase the cells, a negative high voltage of xe2x88x929V is applied to the control gate while a counter voltage about 9V is applied to the bulk region, thereby causing migration of the negative charges from the floating gate to the bulk region (Fouler-Nordheim Tunneling). The threshold voltage of the memory cells whose data are erased becomes lower than those of the memory cells not erased. In a read-out operation, a voltage of about 1V is applied to the drain region, a lower voltage than a threshold voltage of the programmed memory cell also is applied to the control gate and at the same time 0V is applied to the source region so that the programmed memory cell is an xe2x80x9coff-cellxe2x80x9d and the erased memory cell is an xe2x80x9con cellxe2x80x9d.
When a read-out operation on the programmed memory cells or the memory cells whose data are erased is to be performed, a voltage between the threshold voltage of a programmed memory cell and that of a data erased memory cell is applied to a word line connected to a selected memory cell. One approach to resolve the problem whereby the read-out voltage is higher than a voltage of a power supply, boosting the read-out voltage is described in xe2x80x9cA 2.7V only 8 Mbxc3x9716NOR flash memoryxe2x80x9d, symposium on VLSI Circuits Digest of Technical Papers, IEEE 1996.
Recently there is a need for reducing power consumption in the flash memory used in devices such as a handheld communications device or a portable computer operated by a battery. However, the largest obstacle for lowering a used voltage together with very large scale integration (VLSI) is this: The larger the degree of integration, the lower the coefficient of the boosting voltage in the word line during a low-voltage read-out operation.
Some methods for solving this problem have ever been introduced. One of the methods is a process for multi-boosting the word line that enables the fast, low-voltage, read-out operation by increasing the coefficient of the boosting voltage. See (xe2x80x9cQuick Double Bootstrapping Scheme for Word Line of 1.8V Only 16 Mb Flash Memoryxe2x80x9d, the sixth Korean Semiconductor conference, February, 1999). Another is a process in which a charge pump, i.e., a high voltage generator, can be driven on being powered up, so that when a read-out operation is started a high voltage generated from the charge pump can be applied to word lines. This process recently becomes popular in use, since the process enables fast operational speed and lowers power consumption. See (xe2x80x9cOn-chip high voltage generation in NMOS integrated circuits using an improved voltage multiplier techniquexe2x80x9d, J. F. Dickson, IEEE Journal of Solid State Circuits, Jun 1976, pages 374-378). The technologies that use the charge pump to boost the voltage of the word lines on a read-out operation under the low-power voltage are described in an xe2x80x9cOptimization of word-line booster circuits for low-voltage flash memoriesxe2x80x9d, IEEE JSSC, Vol. 34, No. 8, Aug. 1999, pages 1091-1098. Therein are described the advantages of using the charge pump for generating the high voltage, since the circuit region and the operational currents of the charge pump are low compared to other periphery circuit components.
Meanwhile, a row decoder adapted in a NOR type flash memory device must be able to supply different levels of voltages from a negative high-voltage to a positive high-voltage due. This is because of the flash memory as described above. In general, a high voltage refers to a voltage having a potential higher than the potential of the voltage of the power supply. That is, in the case of a 3/3V power supply voltage, about 4.5V can be applied to the selected word line on a read-out operation, about 9V can be applied to the selected word line on the programming operation, and about 9V and xe2x88x929V can be applied to the word line and the bulk region, respectively, on the erasure operation. One circuit supplying such voltages, as well as the row decoder and its associated circuits in conventional device are illustrated in FIG. 1.
In FIG. 1, memory cell sectors 13 and 14 correspond to, for example, ith and jth sectors, respectively, with the total memory cell array divided into a plurality of sectors, each sector comprising 1024 word lines and 512 bit lines having 64(K) (k=1024) byte memory capacity (64(k) (b)ytes=1024*512bits). In a read-out operation or a programmable operation, selection of a word line requires 10 address signals corresponding to 1024 word lines. One of 128 global word lines is selected by a global row decoder 10 and one of eight local word lines allocated to one global word line (128*8=1024) is selected by a local row decoder 15 or 16. The word line driver WD allocated to each word line, drives its associated word line in response to a global word line selection signal GWL supplied from the global row decoder 10, a local word line selection signal PWL supplied from the local row decoder 15 or 16, and a block selection signal BLS supplied from the block decoder 17 or 18. To supply a high voltage (a positive high voltage or a negative high voltage) to a word line in a read-out operation, a program operation or an erase operation, the global row decoder 10 and the local row decoder 15 or 16 are arranged with a level shifter LS for switching the high voltages.
FIG. 2 illustrates the connective relationship between the word line drivers WD0xcx9cWD7 and the LS0 that is one of 128 level shifters embedded in the global row decoder 10. FIG. 3 illustrates the structure of LS0i that is one of eight level shifters embedded in the local decoder 15. In FIG. 2, the voltage terminal VPP represents a positive high voltage for a program operation and VEX represents a negative high voltage for an erase operation. As shown in FIG. 2 and FIG. 3, the high-voltage type PMOS transistors PH1xcx9cPH11 and the high-voltage type NMOS transistors NH1xcx9cNH11 are used to switch the high voltages.
The high-voltage type transistors are the transistors designed to perform the switching function without a physical burden such as a breakdown of an insulating film. Such transistors reinforce the enhancement characteristic of the MOS transistor even if a voltage higher than a voltage of the power supply may be applied to the drain or the source. In a read-out operation or a program operation, the positive high voltage VPP is switched to the corresponding word line, for example WL0i through the high-voltage type PMOS transistors PH1, PH11, and PH3. In an erase operation, the negative high-voltage VEX is switched to the corresponding word line through the high voltage type NMOS transistors NH2 and NH4. The voltages applied according to the respective operation mode is listed in table 1 below:
In the structure of the decoder shown in FIG. 1, the high-voltage type PMOS transistors PH1xcx9cPH11 are made to share their N-type wells that are their bulk regions. That is, all the high-voltage type PMOS transistors relate to decoding are shaped in the one N-type well. Since the high voltage for the read-out or programmable operation is switched via the channel of such a high-voltage type PMOS transistors, the same high voltage is applied to the N-type well of their bulk regions to prevent the voltage drop via the PN junction. Subsequently, the boosting load increases significantly, because the N type well must be boosted, the well being shared from the high-voltage type PMOS transistors of the non-selected decoder regions as well as the high-voltage type PMOS transistors of the selected decoder regions, when the source voltage is being boosted to the high voltage in the read-out or program operation. In particular, the boosting load can be increased because the speed of the read-out operation can be faster only if the voltage of the word line must be boosted faster in the read-out operation. In accordance with a lower source voltage used in the flash memory device, the drop of the read-out operation speed will be increased more according to the increased boosting load.
During the program or erase operation, the burden of boosting the voltage in operation time can be relatively lower than that for the read-out operation, but it should be understood that the high-voltage type PMOS transistors will have their own non-necessary boosting load as long as the N type well, i.e., one bulk region is shared with the high-voltage type PMOS transistors.
In FIG. 4, the conventional circuits are illustrated for generating a high voltage to be supplied to the word line in the read-out operation or the program operation in the flash memory device used with the low source voltage. A small-capacity stand-by high-voltage generator which is activated directly when the flash memory device is powered on, and a large capacity high-voltage generator 23 which is activated when an address transition is detected or when an address transitions are used as shown in FIG. 4, to supply a high voltage VPP to be used in the global row decoder 10. Further, a reference voltage generating circuit 22 is provided for generating a reference voltage VREF applied to non-inverted stages of the comparing amplifiers AMP adapted with the stand-by and active high-voltage generators 21 and 23. However, it is disadvantageous that the capacity or performance of the active charge pump can be reduced and also it can be impossible to separately control the high voltages in the stand-by operation and the active operation. This is because the output terminal of the stand-by high-voltage generator 21 is inter-connected to that of the active high-voltage generator 23 in the high-voltage generating structure in FIG. 4.
Accordingly, it is an object of the present invention to provide a device by which the problem described above can be eliminated and the boosting load can be reduced in the flash memory using the low power voltage.
It is another object of the invention to provide a device for increasing the speed of the read-out operation in the flash memory using the low power voltage.
It is still another object of the invention to provide a device by which the boosting load can be reduced while in the read-out operation, the program operation, and the erase operation in the flash memory using the low power voltage.
It is further still another object of the invention to provide a device for efficiently generating and controlling a high voltage in the flash memory using a low source voltage.
In order to attain the above objects, according to an aspect of the present invention, there is provided a semiconductor memory device including: a plurality of memory cell sectors, each having a plurality of word lines and bit lines and a plurality of memory cells; a plurality of global word lines electrically connected to the word lines via connecting means; sector selection circuits for controlling the connecting means to select the memory cell sector; driver circuits for selectively supplying a voltage according to an operation mode to the global word line via a pull-up transistor therein; a partial row decoder for selectively enabling the voltage according to the operation mode to be supplied to the driver circuits; pre-charging circuits for causing the gate of the pull-up transistor in the driver circuits to be at a predetermined potential before the voltage according to the operation mode is applied to the global word line in response to a predetermined selection signal.
The pull-up transistor is a NMOS transistor for use in high voltages and the driver circuits each further comprise a pull-down transistor between the global word line and ground. The pre-charging circuit comprises a circuit for turning on the pull-down transistor before the voltage according to the operation mode is supplied into the global word line. The connecting means is a depletion transistor. The pre-charging circuits are provided with a power supply at a first high voltage. The partial row decoder supplies the driver circuits with a second high voltage in a read-out operation mode and a third high voltage in a program operation mode. The first, second and third high voltages each is a potential higher than a voltage of the power supply of the semiconductor memory device and a circuit for generating the first high voltage is electrically insulated from a circuit for generating the second high voltage.